The present invention relates generally to signal generating circuits, and, more particularly, to a signal generating circuit which is particularly useful as a chip initialization signal generating circuit for a semiconductor memory device.
In general, when a semiconductor memory device is powered up, an applied power supply voltage is gradually raised to a stable operating voltage level. If the power supply voltage is utilized prior to its having reached its stable operating voltage level, malfunction of the semiconductor memory device may occur. In order to prevent this from occurring, a chip initialization circuit is employed for initializing the circuits within the semiconductor memory device.
A conventional chip initialization circuit includes a time delay circuit and at least one inverter coupled to the output of the time delay circuit. The time delay circuit functions to generate an output signal delayed by a predetermined time period from the time that the power supply voltage is applied thereto. The inverter(s) functions to produce a chip initialization signal by appropriately shaping the output signal of the time delay circuit.
With reference now to FIG. 1, there can be seen an exemplary conventional chip initialization circuit, which includes a time delay circuit 105, a first inverter 110, and a second inverter 25. The time delay circuit 105 is comprised of a diode-connected PMOS transistor 5 connected between a power supply voltage and an output node N1, and a capacitor 10 connected between the output node N1 and ground. The first inverter 110 includes a PMOS transistor 15 and an NMOS transistor 20 connected in series between the power supply voltage and ground, with the gates of the transistors 15, 20 being commonly coupled to the output node N1 of the time delay circuit 105. The second inverter 25 is coupled to the output node of the first inverter 110 and produces a chip initialization signal OVCCH having desired characteristics.
In operation, when the power supply voltage is applied to the circuit, the node N1 is raised to the level of the power supply voltage after a time delay defined by the RC time constant of the time delay circuit 105, it being understood that the diode-connected transistor 5 functions as a resistor element having a resistance R and the capacitor 10 has a capacitance C. When the node N1 reaches the trip point level of the first inverter 110, the chip initialization signal OVCCH is driven to a "high" logic level, to thereby initialize the circuits within the semiconductor memory device (not shown).
The above-described conventional chip initialization signal generating circuit suffers from the following drawback/shortcoming. More particularly, with the conventional chip initialization signal generating circuit, the chip initialization signal OVCCH is sometimes generated before the power supply voltage reaches its stable operating level (i.e., its "full" power supply voltage level), because the node N1 reaches the trip point level of the first inverter 110 before the full power supply voltage level is attained, thereby resulting in malfunction of the semiconductor memory device.
Based on the above, it can be appreciated that there presently exists a need for a chip initialization signal generating circuit which overcomes the above-described shortcomings of the presently available chip initialization signal generating circuits. The present invention fulfills this need.